Thanks. I reckon that giving the clock an individual clean supply is paramount to low jitter. Giving the I/O banks of the Xilinx CPLD it's own 3.3V feed also proved worthwhile. There are only 2 other improvements that I may get to - removing the final 1.8V dc-dc converter & isolating the I2S out (can't do anything to isolate the USB 2.0 at Hi-Speed 480mBits/s)Originally Posted by leo
Sorry I'm late getting back Johnthats good going with the batteries, certainly enough time for most folks, thank you for going to the trouble testing their run time, I'm getting the itch now with buying a Hiface
I like the way you've separated things
Ah, yesWith the pics I just upload them on photo bucket rather than uploading them here, then copy and past the image code link
Reply With Quote
