Squeezebox Duet

[MyNaim]

...
The resistor R104 on the output of the inverter may be better off removed altogether if running a new clock direct to the Xilinx pin42

not sure it has brought something better but it's definitely not a problem to remove it

[janos_904]

Almost 2 years went by since the last post. Leo made a remarkable work, but is it any progress right know on Duet? By chance, I found a clean spdif signal originating from Xilinx chip leg 3 (it goes to the Toslink). I found on the lampizator page a description how to get a signal out from Xilinx (10-100 nF cap in series + resistance of 200 ohm, 75 ohm between GND and signal). It works, and this output is much better. The tweak works on SB3 too. Did somebody similar trick, is any advices of choices of the cap and the resistor types?

[ar-t]

Those resistor values will give the wrong level and impedance.

The shunt resistor has to be larger than the desired output impedance.

[janos_904]

Thank you ar-t for your fast response. What values (C, R1?, R2?) do you recommend to get a good impedance? This is lampizator's description (maybe I misunderstood it?):

"4. Middle red circle shows the real source of S/PDIF signal.
Just gently desolder R102 attached to pin 3 of the XILINX. Solder a capacitor - one leg to the lower soldering pad left after removal of R102. It will be directly connected to Pin 3 of the Xilinx. The other leg of that cap (any foil type like MKP, MKT, MKS, or even a ceramic, size between 10 nF and 220 nF, ) connects to a 200 Ohm resistor. The other end of this resistor connects to the center pin of the RCA with SPDIF. First - cut off the RCA center pin from the pcb and float it. Last point: solder across the RCA - between center and GND surrounding golden frame - a resistor 75 Ohms. (or 58 Ohms if you want to be close to real RCA and coax impedance). "

[ar-t]

No, you did not misunderstand. I think someone else is just wrong.

Off the top of my head.......without aid of calculator, or even scratch pad................try 220R and 100R. That will get you closer.

But, you know how to calculate the resistance of 2 resistors in parallel. That will get you close.

In addition, I bet you can figure out a voltage divider. If you want to get really technical, you need to know the output Z of the chip where you get the signal from. That depends on the logic family, etc., and operating voltage. (R goes up, as rail voltage goes down.)

Don't know who originally came up with the values. I bet he neglected all of that. Or, maybe he thought it was not important.

I won't say who, but I bet most here will know who I am talking about, in the following.

A "competitor" copied the values in the TI data sheet. Ooops...........TI also was wrong! The impedance was wrong, and the voltage was twice what it should have been. I believe they corrected it. But still wrong in the data sheet, even today.

So, just because it is in a data sheet........well, they are as good as a lot of the free advice you get on the 'Net!

[lenta]

I would realy like to get your comments about this direct xilinx spdif output.
Becouse I read somewere that its bad idea, but it wasnt clear why.

If one separates the clock and SPDIF functions, totally, what happens to the SPDIF signal?

If you do it properly, the deterministic jitter goes completely away. The random jitter can be much lower, depending on the quality of the clock.

Is it proper way? At least it seperates spdif from clock of the 74hcu chip.

Regards,
Martin

[Marco]

Hi Martin,

Welcome to AoS!

Before you go any further, however, please read this thread and comply with the request therein: http://theartofsound.net/forum/showthread.php?t=17333

All newbies must pop into the Welcome area and say hello - cheers!

Marco.

[ar-t]

I would not try to drive anything, other than another gate, with the output of a FPGA. They are not designed to drive tons of current.

A single picogate D flip-flop can do it. Also reclocks the signal.