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Thread: Reclocker (i2s ps jitter)

  1. #11
    Join Date: Feb 2008

    Location: http://www.homehifi.co.uk

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    As long as users of my DACs with the latest firmware upgrade don't get carried away with using this clock, I am not bothered. My own clocking process relies on the clock in the signal to generate an accurate reference. If that incoming clocked signal is no longer original, some or all of the extra data that is extracted from the valid audio signal may get washed away by a third party external clock if that external clock starts amending the clock phase and period. Over eager reclocking is one of the prime reason why digital audio can sound so synthetic through some DACs. A lot of the "goodness" in the signal can get discarded after being incorrectly identified as noise or a signal error. Soundstage, or the lack of it, tends to be a dead give away of an over active clock.

  2. #12
    Join Date: Aug 2016

    Location: France

    Posts: 198
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    Quote Originally Posted by StanleyB View Post
    As long as users of my DACs with the latest firmware upgrade don't get carried away with using this clock, I am not bothered. My own clocking process relies on the clock in the signal to generate an accurate reference. If that incoming clocked signal is no longer original, some or all of the extra data that is extracted from the valid audio signal may get washed away by a third party external clock if that external clock starts amending the clock phase and period. Over eager reclocking is one of the prime reason why digital audio can sound so synthetic through some DACs. A lot of the "goodness" in the signal can get discarded after being incorrectly identified as noise or a signal error. Soundstage, or the lack of it, tends to be a dead give away of an over active clock.
    Stanley,

    This is for i2s signals..basically the jittery clocks from RPI (bclk . lrclk) is replaced with a high quality low jitter clock . DATA is (buffered) and then synchronized using this new clock...how can the signal loose any info ?? We have measured the RMS jitter of the MCLK (ours) at 3.081ps but the floor of the oscilloscope is 1ps...so we think that jitter is actually lower. Any DAC will benefit from a better (low jitter/phase noise ) clock. Including yours.

  3. #13
    Join Date: Feb 2008

    Location: http://www.homehifi.co.uk

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    Quote Originally Posted by Audiohdwr View Post
    Stanley,

    This is for i2s signals..basically the jittery clocks from RPI (bclk . lrclk) is replaced with a high quality low jitter clock . DATA is (buffered) and then synchronized using this new clock...how can the signal loose any info ?? We have measured the RMS jitter of the MCLK (ours) at 3.081ps but the floor of the oscilloscope is 1ps...so we think that jitter is actually lower. Any DAC will benefit from a better (low jitter/phase noise ) clock. Including yours.
    Been there, done it, and eventually ended up giving customers the option to select how the clocks connect or interact with each other. The famous option-3 in some of my firmwares eventually settled the argument for me.
    Good luck with your endeavour. But there is a lot to be said against brickwalling the clock. Very fine detail on the boundaries of data errors are easily ignored by a fixed clock. One only has to listen to the kind of detail my SEG can reproduce in order to get an idea of what has often been stripped out by most other DACs. The smoking gun turned out to be the fixed clock.

  4. #14
    Join Date: Aug 2016

    Location: France

    Posts: 198
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    Quote Originally Posted by StanleyB View Post
    Been there, done it, and eventually ended up giving customers the option to select how the clocks connect or interact with each other. The famous option-3 in some of my firmwares eventually settled the argument for me.
    Good luck with your endeavour. But there is a lot to be said against brickwalling the clock. Very fine detail on the boundaries of data errors are easily ignored by a fixed clock. One only has to listen to the kind of detail my SEG can reproduce in order to get an idea of what has often been stripped out by most other DACs. The smoking gun turned out to be the fixed clock.
    Hi again,
    I am not sure I understand your statement , clocks do not connect or interact to eachother. Furthermore DATA (on i2s bus( does not have "fine details" ..its just bits (0/1)
    Frankly speaking , I think that your "famous option-3" might be nothing but marketing talk.

  5. #15
    Join Date: Aug 2016

    Location: France

    Posts: 198
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    A very solid contribution to the forum about our hardware from LoveJoy.

    http://theartofsound.net/forum/showt...berry-Pi/page2

  6. #16
    Join Date: Nov 2010

    Location: Coventry

    Posts: 3,039
    I'm Will.

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    Quote Originally Posted by Audiohdwr View Post
    correct Rich,
    you can refer to the image i posted in an earlier post... you will see the KALI reclocker sitting between our Sparky SBC and Piano DAC.
    as you can see, we opted for an open top/bottom enclosure, not a closed case... helps with airflow and only the spacers have to adjusted in case you want to add or remove a board.

    for testing, you can please PM me.

    cheers
    Andre
    Hi Andre, just to confirm, is this compatible with a Pi (2 in my case), and it's associated DAC boards? IQ, audiophonics etc...?
    Cheers, Will

  7. #17
    Join Date: Aug 2016

    Location: France

    Posts: 198
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    Hi Will,
    yes you can use the KALI with RPI 2 as LoveJoy did (see his complete review in the link above), on the other hand, this current version of KALI wont work with Master DACs... only Slaves...

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